1. Technical Field
The present invention relates to electronic devices.
2. Related Art
Because stored content disappears from a DRAM (Dynamic RAM) if that DRAM is not accessed for a certain amount of time, it is necessary to update (hereinafter, “refresh”) the stored content at a set cycle (JP-A-2007-233633 and so on). For example, in the case where all of the cells (storage regions) of which a DRAM is configured are to be refreshed within a predetermined period (64 ms), it is necessary for a controller that controls the DRAM to issue a refresh command to the DRAM an average of once every 7.8 μs (when there are 8,192 cells or columns).
However, it is not absolutely necessary to carry out a refresh once every 7.8 μs; on the contrary, the refresh interval can be set freely as long as all of the cells are ultimately refreshed within the predetermined period (64 ms). Hereinafter, performing refreshes at equal intervals will be called “distributed refreshing”, whereas performing refreshes in a concentrated manner in shorter period of time than the distributed refreshing will be called “concentrated refreshing”.
Incidentally, the aforementioned refresh operations require a comparatively long time, and because the DRAM cannot be accessed during that time, the performance of the DRAM is affected greatly by the timing of the refresh operations.